1. Field of the Invention
The present invention relates generally to a scaled MOSFET device and its fabrication method and, more particularly, to a nanometer-gate MOSFET device and its fabrication method for ultra-large-scale integration (ULSI).
2. Description of Related Art
The metal-oxide-semiconductor (MOS) field-effect transistors including n-channel MOSFET and p-channel MOSFET in CMOS integrated-circuits are scaled very rapidly based on the known scaling rule in order to gain densityxc2x7speedxc2x7power product. Basically, the surface dimensions of a device including device channel length and device channel width can be directly scaled by an advanced lithographic technique, and the device isolation and contact areas must also be scaled accordingly in order to increase the packing density of the integrated-circuits. However, as a gate length of a MOSFET device is further scaled down below 0.13 xcexcm, there are several issues encountered: a larger tunneling current between the channel and the elongated conductive-gate layer near the trench corners in the channel-width direction; a larger tunneling current between the elongated conductive-gate layer and the source/drain diffusion regions; a higher source/drain junction capacitance due to the pocket or halo implant; a poorer subthreshold slope or off leakage current due to the improper profile formed under the gate region; and a contact integrity for shallow source/drain diffusion regions. These issues become serious as the gate length is scaled below 0.13 xcexcm and the gate-oxide thickness is smaller than 25 Angstroms.
Several methods had been proposed to improve or alleviate a part of the issues as described above. For examples, U.S. Pat. No. 5,966,615 had described a process for forming a shallow-trench-isolation (STI) structure to eliminate a larger tunneling current between the channel and the elongated conductive-gate layer near the trench corners in the channel-width direction, however the active region of a device is reduced by the formed oxide spacer; U.S. Pat. No. 5,614,430 had proposed a process for forming a MOSFET device with an anti-punchthrough ion-implantation through an opened gate region to reduce the parasitic source/drain junction capacitances due to a pocket or halo implant, however the other issues as stated are overlooked and the process steps for forming a MOSFET device are critical for practical applications; U.S. Pat. No. 5,856,225 had described a process of forming a MOSFET device with a self-aligned, ion-implanted channel region after source and drain formation, however a shallow-trench-isolation (STI) used is difficult to eliminate the larger leakage current between the channel and the elongated conductive-gate layer near the trench corners in the channel-width direction and between the source/drain diffusion region and the elongated conductive-gate layer through the overlapping area, moreover the metal-silicide layer over each of the source/drain diffusion regions are experienced by several thermal cycles such as the gate-oxide formation, the poly-gate formation, and the poly-gate silicidation and the integrity of source/drain contacts becomes a major issue; U.S. Pat. No. 5,955,759 had described the elevated conductive layers over the source/drain diffusion regions by using a selective epitaxy technique to reduce the contact resistance for shallow source/drain junctions, however the high parasitic capacitances between a T-shaped gate and the elevated source/drain conductive layers become a drawback for a high-performance MOSFET device.
It is, therefore, an objective of the present invention to offer a MOSFET device and its manufacturing method for eliminating and alleviating the issues encountered.
Accordingly, the present invention discloses a basic MOSFET device structure and its manufacturing method for forming a nanometer-gate MOSFET device. The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure for eliminating the tunneling current between the channel and the elongated conductive-gate layer near the trench corners in the channel-width direction; a self-aligned source/drain diffusion structure with a buffer region to reduce the overlapping area between the elongated conductive-gate layer and the lightly-doped source/drain diffusion regions and with a offset region for forming a self-aligned silicidation source/drain contact; and a highly conductive-gate structure for forming an implant region in a central portion of the channel to eliminate the parasitic source/drain junction capacitances and the punch-through effect.
The shallow-trench-isolation structure of the present invention comprises a first conductive layer over a gate-dielectric layer being formed over the channel region and the first raised field-oxide layer being formed in the shallow-trench-isolation region under the elongated conductive-gate layer. The self-aligned source/drain diffusion structure comprises a buffer-oxide layer being formed over each sidewall of the gate region and on each side portion of the gate region for forming the lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming the heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers to define the self-aligned source/drain silicidation contacts. The highly conductive-gate structure comprises a pair of second conductive sidewall spacers being formed over each inner sidewall of the elongated-gate region and on a portion of a flat surface formed by the first conductive layer and the first raised field-oxide layers for forming an implant region in a self-aligned manner and a composite conductive gate structure including a salicide-gate, a polycide-gate, or a metal-gate being formed over the flat surface formed by the first conductive layer and the first raised field-oxide layers.